Verilog HDL错误Error (10110)
程序如下：
module miaobiao(clk_100Hz,rst,start,min,sec,ssec);
input clk_100Hz;
input rst,start;
output [7:0] min;
output [7:0] sec;
output [7:0] ssec;
reg[7:0] min;
reg[7:0] sec;
reg[7:0] ssec;
always@(posedge clk_100Hz or posedge rst or negedge start)
begin
if(rst)
begin
min[7:0]