The memory controller is the main function of coordination of CPU and function of IP check external memory data exchange. Static random access memory operating mode and control mode of different manufacturers, different products as well as their mode of operation. Generalize common timing control mode, control the hardware IP behavior level, FPGA integrated wiring layout method and process. Design is the meaning of. The design of a technical route from the outside to the inside, namely first on DDR3function analysis, relative temporal relation and data transfer relationship, then according to the communication protocol through in-depth study on control action of mathematical model, mathematical model and hardware structure relationship, complete the hardware interface module to cooperate with the hardware circuit to control the realization of its functions, complete CPU and function of IP nucleus with an external memory for data exchange, data access.