下列VHDL语言什么意思?求注解
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY func IS
PORT a :IN STD_LOGIC_VECTOR (0 to 2 ) ;
m :OUT STD_LOGIC_VECTOR (0 to 2 ) ;
END ENTITY func
ARCHITECTURE demo OF func IS
FUNCTION sam(x ,y ,z :STD_LOGIC) RETURN STD_LOGIC IS
BEGIN
RETURN ( x AND y ) OR y ;
END FUNCTION sam
BEGIN
PROCESS ( a )
BEGIN
m(0)