LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY test IS
PORT(
F:IN STD_LOGIC;
CLK:IN STD_LOGIC;
CARRY :IN STD_LOGIC;
RIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_LOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_HIGH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END test;
ARCHITECTURE RTL OF test IS
SIGNAL F_IN:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(CLK,F,CARRY)
BEGIN
F_IN